The present invention relates to an R-2R type D/A converter circuit which is used commonly in two different circuits, in a time-sequential manner, and is suitable as an analog signal source for these two circuits.
FIG. 1 shows a conventional R-2R type D/A converter circuit of n-bit construction.
In this Figure, digital input terminals 11.sub.0 to 11.sub.n-1, which receive sequentially weighted n-bit digital signals D.sub.0 to D.sub.n-1, are connected to first ends of resistors 2R.sub.0 to 2R.sub.n-1. Resistors R.sub.0 to R.sub.n-2 are connected between second ends of resistors 2R.sub.0 to 2R.sub.n-1. Resistor 2R is connected between a junction of resistors 2R0 and R0 and the ground. Analog signal Aout, which corresponds to digital signals D.sub.0 to D.sub.n-1, is output from a junction of resistors 2R.sub.n-1 and R.sub.n-2. The resistance value of each of resistors 2R and 2R.sub.0 to 2R.sub.n-1 is twice that of each of resistors R.sub.0 to R.sub.n-2.
The D/A converter as shown in FIG. 1 is combined with two analog circuits, as shown in FIG. 2, in which an output signal of the D/A converter is selectively supplied to the two analog circuits. An input terminal of D/A converter circuit 12 receives n-bit digital signals D.sub.0 to D.sub.n-. An output terminal of D/A converter circuit 12 is connected to first ends of first and second switches (e.g., analog switches) 13.sub.1 and 13.sub.2. The second ends of switches 13.sub.1 and 13.sub.2 are connected to input terminals of first and second analog circuits 14.sub.1 and 14.sub.2. Switches 13.sub.1 and 13.sub.2 are turned on/off by complementary logic level signals 1 and 2, so that output signal A.sub.out of D/A converter circuit 12 is fed selectively to analog circuit 14.sub.1 or to analog circuit 14.sub.2. Switches 13.sub.1 and 13.sub.2 are employed in order to eliminate the following problem:
In the case where, for example, the input impedance of analog circuit 14.sub.1 is higher than the output impedance of D/A converter circuit 12, while the input impedance of analog circuit 14.sub.2 is lower than the output impedance of D/A converter circuit 12, if the output terminal of D/A converter circuit 12 is connected directly to the input terminals of analog circuits 14.sub.1 and 14.sub.2, output signal A.sub.out of D/A converter circuit 12 is adversely affected by analog circuit 14.sub.2. Namely, by electrically separating the input terminals of analog circuits 14.sub.1 and 14.sub.2 by using switches 13.sub.1 and 13.sub.2, output signal A.sub.out of D/A converter circuit 12 is protected against the influence of analog circuit 14.sub.2.
The level of analog signal A.sub.out, however, varies in accordance with the digital input. Thus, if each switch 13.sub.1, 13.sub.2 is constituted by a transfer gate in which P-channel type MOS transistor and N-channel type MOS transistor are connected in parallel, the impedance of each MOS transistor is varied by a backgate bias effect, so that analog signal A.sub.out output from D/A converter circuit 12 is adversely affected.
Alternatively, a multiplexer is used to select one of the two analog circuits. Since, however, a multiplexer is generally constituted by an active element, the input impedance is varied non-linearly, in accordance with a voltage applied to the multiplexer. Therefore, the analog signal fed from the D/A converter circuit is also adversely affected.
As stated above, in the case where an output signal of a conventional R-2R type D/A converter circuit is supplied to two analog circuits, in a time-sequential manner, then a switch or multiplexer must be provided in an analog signal line. The presence of this switch or multiplexer, however, adversely affect an output analog signal of the analog circuit system.